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Features
* 400 MHz ARM926EJ-STM ARM(R) Thumb(R) Processor
- 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU
* Memories
- 4-port, 4-bank DDR2/LPDDR Controller - External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash(R), SLC NAND Flash with ECC - One 64-KByte internal SRAM, single-cycle access at system speed or processor speed through TCM interface - One 64-KByte internal ROM, embedding bootstrap routine Peripherals - Universal Video Decoder provides decoding at up to 30 fps at D1 (720 x 576 pixels) or WVGA (800 x 480) resolution - LCD Controller supporting STN and TFT displays up to 1280*860 - ITU-R BT. 601/656 Image Sensor Interface - Dual High Speed USB Host and a High Speed USB Device with On-Chip Transceivers - 10/100 Mbps Ethernet MAC Controller - Two High Speed Memory Card Hosts (SDIO, SDCard, e.MMC and CE ATA) - AC'97 controller - Two Master/Slave Serial Peripheral Interfaces - Two Three-channel 16-bit Timer/Counters - Two Synchronous Serial Controllers (I2S mode) - Four-channel 16-bit PWM Controller - Two Two-wire Interfaces - Four USARTs with ISO7816, IrDA, Manchester and SPI modes - 8-channel 10-bit ADC with 4-wire Touch Screen support Cryptography - TRNG True Random Number Generator - AES256-, 192-, 128-bit Key Algorithm - TDES Compliant with FIPS PUB 46-3 Specifications - SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2 System - 133 MHz twelve 32-bit layer AHB Bus Matrix - 39 DMA Channels - Boot from NAND Flash, SDCard, DataFlash(R) or serial DataFlash - Reset Controller with on-chip Power-on Reset - Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators - Internal Low-power 32 kHz RC Oscillator - One PLL for the system and one 480 MHz PLL optimized for USB High Speed - Two Programmable External Clock Signals - Advanced Interrupt Controller and Debug Unit - Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock I/O - Five 32-bit Parallel Input/Output Controllers - 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input Package - 324-ball TFBGA, pitch 0.8 mm
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AT91 ARM Thumb-based Microcontrollers AT91SAM9M11 Preliminary Summary
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NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office.
6437BS-ATARM-26-Apr-10
1. Description
The AT91SAM9M11 is a multimedia enabled mid-range ARM926-based embedded MPU running at 400MHz, combining user interfaces, video playback and connectivity. It includes hardware video decoder, LCD Controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. The hardware video decoder supports H.264, MPEG-4, MPEG-2, VC-1, H.263 up to D1 (720 x 576 pixels) or WVGA (800 x 480) resolutions at 30 frames per second (fps). The SAM9M11 also provides hardware image post-processing, such as image scaling, color conversion and image rotation. The AT91SAM9M11 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 39 DMA channels, a dual external bus interface and distributed memory including a 64KByte SRAM which can be configured as a tightly coupled memory (TCM) sustains the high bandwidth required by the processor and the high speed peripherals. On-chip hardware accelerators with DMA support enable high-speed data encryption and authentication of the transferred data or application. Supported standards are up to 256-bit AES, FIPS PUB 46-3 compliant TDES and FIPS Publication 180-2 compliant SHA1 and SHA256. A True Random Number Generator is embedded for key generation and exchange protocols. The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing. The AT91SAM9M11 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes. The AT91SAM9M11 device is particularly well suited for media-rich displays and control panels in home and commercial buildings, POS terminals, entertainment systems, internet appliances and medical applications.
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AT91SAM9M11
6437BS-ATARM-26-Apr-10
Figure 2-1.
NT RS T TD I TD O TM TS CK RT CK
JTA GS
BM
S
HF S HH DPA SD , PA HFS ,H DM HS A VB DM G A DF S DH DP/H SD FS P/H DP H SD B,DF LC PB SD D LC D0 ,D M HS /H D -L D LV C M/ FSD CD SYN DD 2 HH MB LD DO C,L 3 SD DT C MB LC EN CK DH SY DP ,LC NC I SI WR DCC _ ,L ID SI O-I CD _ S M IS PCK I_D OD I_ 11 IS H I_ SY IS V N I_MSYN C CC ET K X ET C X K-E EC EN RX R -E C ER S-E TX K E EX C R RX ER- OL ET 0-E ERX X RX DV E0 M -ET 3 EM DC X3 DI O
M CI M 0_D C I0 A0 _C -M M DA CI0 C ,M _ M I0_ CI DA C I1 CK 1_C 7 _D ,M D A0 CI A -M 1_ CI CK 1_ DA TW 7 TW D0 CK0 TW -D CT TW 1 C S RT 0- K1 S CT SC 0-R S3 KT RD 0-S S3 XC TX 0-R K3 D0 DX PW -TX 3 D3 M 0PW TC M LK 3 TI 0-T O A0 CL T-K IO TIO 2 TC B0 A2 L -T TI K3 IO B OTI A3 TCL 2 OB3 TIO K5 -T A5 IO B NP 5 NP CS C3 NP S2 NP CS C1 SP S0 C MK O M SI TK ISO 0 TF -TK TD 0-T 1 F R0 1 D0 -TD RF -RD1 0 RK -R 1 0- F1 AC RK1 AC 97C 9K AC 7F 9S AC 7RX TS 97 AT DT X R AD IG 0 AD XP 1 AX D2 M Y GP AD AD3 P Y 4 TS -GPA M A DV D7 RE V DD F A GN NA D
6437BS-ATARM-26-Apr-10
EL
2. Block Diagram
TST In-Circuit Emulator PA LCD EMAC 8-CH DMA ISI HS EHCI USB HOST DMA DMA DMA DMA DMA HS USB PB
System Controller
JTAG / Boundary Scan
PIO
HS Transceiver
HS Transceiver
PCK0-PCK1
FIQ IRQ
AIC ARM926EJ-S
PIO
DBGU
DRXD DTXD DCache ICache MMU 32Kbytes 32K bytes ITCM DTCM Bus Interface
PDC
DDR_A0-DDR_A13 DDR_D0-DDR_D15 DDR_VREF DDR_DQM[0..1] DDR_DQS[0..1]
PLLRCA
PLLA I
SRAM 64KB
AT91SAM9M11 Block Diagram
PLLUTMI PMC D
DDR2 LPDDR
XIN XOUT
OSC12M
DDR_CS DDR_CLK,#DDR_CL DDR_CKE DDR_RAS, DDR_CAS DDR_WE DDR_BA0, DDR_BA1
WDT
PIT
RC
4 GPBR
OSC 32K
EBI
RTT
XIN32 XOUT32 SHDN WKUP
SHDC
RTC
Multi-Layer AHB Matrix
VDDBU NRST
POR
RSTC
DDR2/ LPDDR/ SDRAM Controller
VDDCORE TDES AES PDC PDC TRNG Peripheral Bridge ROM 64KB SHA
POR
PIOA
Peripheral DMA Controller
PIOD
PIOB
PIOE
Video Decoder + Post Processing
PIOC
NandFlash Controller ECC
APB
CF PDC SPI0 SPI1 PDC PDC PDC AC97 8-CH 10Bit ADC TouchScreen
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18 A16/BA0 A17/BA1 NCS1/SDCS SDCK, #SDCK, SDCK RAS, CAS SDWE, SDA10 DQM[0..1] DQS[0..1] NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 NCS0 NANDOE, NANDWE
FIFO TWI0 TWI1 4-CH PWM TC0 TC1 TC2 TC3 TC4 TC5
MCI0/MCI1 SD/SDIO CE ATA
PDC USART0 USART1 USART2 USART3
SSC0 SSC1
Static Memory Controller
PIO
D16-D31 NWAIT DQM[2..3] A19-A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 NCS2 NCS3/NANDCS
SPI0_, SPI1_
SSC0_, SSC1_
AT91SAM9M11
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3. Signal Description
Table 3-1 gives details on the signal names classified by peripheral. Table 3-1.
Signal Name
Signal Description List
Function Type Power Supplies Active Level Reference Voltage Comments
VDDIOM0 VDDIOM1 VDDIOP0 VDDIOP1 VDDIOP2 VDDBU VDDANA VDDPLLA VDDPLLUTMI VDDOSC VDDCORE VDDUTMIC VDDUTMII GNDIOM GNDIOP GNDCORE GNDOSC GNDBU GNDUTMI GNDANA
DDR2 I/O Lines Power Supply EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Peripherals I/O Lines Power Supply ISI I/O Lines Power Supply Backup I/O Lines Power Supply Analog Power Supply PLLA Power Supply PLLUTMI Power Supply Oscillator Power Supply Core Chip Power Supply UDPHS and UHPHS UTMI+ Core Power Supply UDPHS and UHPHS UTMI+ interface Power Supply DDR2 and EBI I/O Lines Ground Peripherals and ISI I/O lines Ground Core Chip Ground PLLA, PLLUTMI and Oscillator Ground Backup Ground UDPHS and UHPHS UTMI+ Core and interface Ground Analog Ground
Power Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Clocks, Oscillators and PLLs
1.65V to 1.95V 1.65V to 1.95V or 3.0V to3.6V 1.65V to 3.6V 1.65V to 3.6V 1.65V to 3.6V 1.8V to 3.6V 3.0V to 3.6V 0.9V to 1.1V 0.9V to 1.1V 1.65V to 3.6V 0.9V to 1.1V 0.9V to 1.1V 3.0V to 3.6V
XIN XOUT XIN32 XOUT32 VBG PCK0 - PCK1
Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Bias Voltage Reference for USB Programmable Clock Output
Input Output Input Output Analog Output
(1)
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AT91SAM9M11
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AT91SAM9M11
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Active Level Reference Voltage Comments
Shutdown, Wakeup Logic Driven at 0V only. 0: The device is in backup mode 1: The device is running (not in backup mode). Accept between 0V and VDDBU.
SHDN
Shut-Down Control
Output
VDDBU
WKUP
Wake-Up Input
Input ICE and JTAG
VDDBU
TCK TDI TDO TMS JTAGSEL RTCK
Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Return Test Clock
Input Input Output Input Input Output Reset/Test
VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDBU VDDIOP0
No pull-up resistor, Schmitt trigger No pull-up resistor, Schmitt trigger
No pull-up resistor, Schmitt trigger Pull-down resistor (15 k).
NRST
Microcontroller Reset(2)
I/O
Low
VDDIOP0
Open-drain output, Pull-Up resistor (100 k), Schmitt trigger Pull-down resistor (15 k), Schmitt trigger Pull-Up resistor (100 k), Schmitt trigger must be connected to GND or VDDIOP0.
TST NTRST BMS
Test Mode Select Test Reset Signal Boot Mode Select
Input Input Input Debug Unit - DBGU
VDDBU VDDIOP0 VDDIOP0
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output Advanced Interrupt Controller - AIC
(1) (1)
IRQ FIQ
External Interrupt Input Fast Interrupt Input
Input Input
(1) (1)
PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOE PA0 - PA31 PB0 - PB31 Parallel IO Controller A Parallel IO Controller B I/O I/O
(1)
Pulled-up input at reset (100k)(3), Schmitt trigger Pulled-up input at reset (100k)(3), Schmitt trigger
(1)
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6437BS-ATARM-26-Apr-10
Table 3-1.
Signal Name PC0 - PC31 PD0 - PD31 PE0 - PE31
Signal Description List (Continued)
Function Parallel IO Controller C Parallel IO Controller D Parallel IO Controller E Type I/O I/O I/O Active Level Reference Voltage
(1)
Comments Pulled-up input at reset (100k)(3), Schmitt trigger Pulled-up input at reset (100k)(3), Schmitt trigger Pulled-up input at reset (100k)(3), Schmitt trigger
(1)
(1)
DDR Memory Interface - DDR2/LPDDR Controller DDR_D0 DDR_D15 DDR_A0 DDR_A13 DDR_CLK#DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RASDDR_CAS DDR_DQM[0..1] DDR_DQS[0..1] DDR_BA0 DDR_BA1 DDR_VREF Data Bus Address Bus DDR differential clock input DDR Clock Enable DDR Chip Select DDR Write Enable Row and Column Signal Write Data Mask Data Strobe Bank Select Reference Voltage I/O Output Output Output Output Output Output Output Output Output Input External Bus Interface - EBI D0 -D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low VDDIOM1 VDDIOM1 VDDIOM1 Pulled-up input at reset 0 at reset High Low Low Low VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 Pulled-up input at reset 0 at reset
EBI - Static Memory Controller - SMC NCS0 - NCS5 NWR0 - NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output Low Low Low Low Low VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1
EBI - CompactFlash Support CFCE1 - CFCE2 CFOE CFWE CFIOR CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read Output Output Output Output Low Low Low Low VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1
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AT91SAM9M11
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AT91SAM9M11
Table 3-1.
Signal Name CFIOW CFRNW CFCS0 -CFCS1
Signal Description List (Continued)
Function CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines Type Output Output Output Low Active Level Low Reference Voltage VDDIOM1 VDDIOM1 VDDIOM1 Comments
EBI - NAND Flash Support NANDCS NANDOE NANDWE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable Output Output Output Low Low Low VDDIOM1 VDDIOM1 VDDIOM1
EBI - DDR2/SDRAM/LPDDR Controller SDCK,#SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 DQS[0..1] DQM[0..3] DDR2/SDRAM differential clock DDR2/SDRAM Clock Enable DDR2/SDRAM Controller Chip Select Bank Select DDR2/SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Data Strobe Write Data Mask Output Output Output Output Output Output Output Output Output Low Low High Low VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1
High Speed Multimedia Card Interface - HSMCIx MCIx_CK MCIx_CDA MCIx_DA0 MCIx_DA7 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data I/O I/O I/O
(1) (1)
(1)
Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send I/O Output Input Output Input Synchronous Serial Controller - SSCx TDx RDx TKx RKx TFx RFx SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
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6437BS-ATARM-26-Apr-10
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Active Level Reference Voltage Comments
AC97 Controller - AC97C AC97RX AC97TX AC97FS AC97CK AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Input Output Output Input Time Counter - TCx TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O
(1) (1) (1) (1) (1) (1) (1)
Pulse Width Modulation Controller - PWM PWMx Pulse Width Modulation Output Output
(1)
Serial Peripheral Interface - SPIx_ SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1SPIx_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low
(1) (1) (1) (1)
(1)
Two-Wire Interface TWDx TWCKx Two-wire Serial Data Two-wire Serial Clock I/O I/O USB Host High Speed Port - UHPHS HFSDPA HFSDMA HHSDPA HHSDMA HFSDPB HFSDMB HHSDPB HHSDMB USB Host Port A Full Speed Data + USB Host Port A Full Speed Data USB Host Port A High Speed Data + USB Host Port A High Speed Data USB Host Port B Full Speed Data + USB Host Port B Full Speed Data USB Host Port B High Speed Data + USB Host Port B High Speed Data Analog Analog Analog Analog Analog Analog Analog Analog VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDUTMII Multiplexed with DFSDP Multiplexed with DFSDM Multiplexed with DHSDP Multiplexed with DHSDM
(1) (1)
USB Device High Speed Port - UDPHS DFSDM DFSDP DHSDM DHSDP USB Device Full Speed Data USB Device Full Speed Data + USB Device High Speed Data USB Device High Speed Data + Analog Analog Analog Analog VDDUTMII VDDUTMII VDDUTMII VDDUTMII
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AT91SAM9M11
6437BS-ATARM-26-Apr-10
AT91SAM9M11
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Ethernet 10/100 Active Level Reference Voltage Comments
ETXCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO
Transmit Clock or Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output
Input Input Output Output Output Input Input Input Input Input Output I/O
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
MII only, REFCK in RMII MII only
ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII
MII only MII only
Image Sensor Interface ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image sensor Reference clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data clock Input output input input input LCD Controller - LCDC LCDD0 LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCDPWR LCDMOD LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control LCD panel Power enable control LCD Modulation signal Output Output Output Output Output Output Output Output VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2
Touch Screen Analog-to-Digital Converter AD0XP AD1XM AD2YP Analog input channel 0 or Touch Screen Top channel Analog input channel 1 or Touch Screen Bottom channel Analog input channel 2 or Touch Screen Right channel Analog Analog Analog VDDANA VDDANA VDDANA Multiplexed with AD0 Multiplexed with AD1 Multiplexed with AD2
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6437BS-ATARM-26-Apr-10
Table 3-1.
Signal Name AD3YM
Signal Description List (Continued)
Function Analog input channel 3 or Touch Screen Left channel Analog Inputs ADC Trigger ADC Reference Type Analog Analog Input Analog Active Level Reference Voltage VDDANA VDDANA VDDANA VDDANA Comments Multiplexed with AD3
GPAD4-GPAD7 TSADTRG TSADVREF Notes:
1. Refer to peripheral multiplexing tables in Section 9.4 "Peripheral Signals Multiplexing on I/O Lines" for these signals. 2. When configured as an input, the NRST pin enables asynchronous reset of the device when asserted low. This allows connection of a simple push button on the NRST pin as a system-user reset. 3. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column "Reset State" of the peripheral multiplexing tables.
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AT91SAM9M11
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AT91SAM9M11
4. Package and Pinout
The AT91SAM9M11 is delivered in a 324-ball LFBGA package.
4.1
Mechanical Overview of the 324-ball LFBGA Package
Figure 4-1 shows the orientation of the 324-ball LFBGA Package Figure 4-1. Orientation of the 324-ball LFBGA Package
Bottom VIEW
V U T R P N M L K J H G F E D C B A
12
3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18
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4.2
324-ball TFBGA Package Pinout
AT91SAM9M11 Pinout for 324-ball BGA Package
Pin E10 E11 E12 E13 E14 E15 E16 E17 E18 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 H1 H2 H3 Signal Name NANDWE DQS1 D13 D11 A4 A8 A9 A7 VDDCORE PD22 PD24 SHDN PE1 PE3 VDDIOM1 PC19 PC14 PC4 NCS1/SDCS NRD SDWE A0/NBS0 A1/NBS2/NWR2 A3 A6 A5 A2 PD25 PD23 PE6 PE0 PE2 PE8 PE4 PE11 GNDCORE VDDIOM1 VDDIOM1 VDDCORE VDDCORE DDR_DQM0 DDR_DQS1 DDR_BA1 DDR_BA0 DDR_DQS0 PD26 PD27 VDDIOP1 Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Signal Name PE21 PE23 PE26 PE22 PE24 PE25 PE27 PE28 VDDIOP0 VDDIOP0 GNDIOM GNDIOM VDDIOM0 DDR_A7 DDR_A8 DDR_A9 DDR_A11 DDR_A10 PA0 PE30 PE29 PE31 PA2 PA4 PA8 PD2 PD13 PD29 PD31 VDDIOM0 VDDIOM0 DDR_A1 DDR_A3 DDR_A4 DDR_A6 DDR_A5 PA1 PA5 PA6 PA7 PA10 PA14 PB14 PD4 PD15 NRST PB11 PB25 Pin P10 P11 P12 P13 P14 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 Signal Name TMS VDDPLLA PB20 PB31 DDR_D7 DDR_D3 DDR_D4 DDR_D5 DDR_D10 PA18 PA20 PA24 PA30 PB4 PB13 PD0 PD9 PD18 TDI RTCK PB22 PB29 DDR_D6 DDR_D1 DDR_D0 HHSDMA HFSDMA PA22 PA25 PA26 PB0 PB6 PB16 PD1 PD11 PD19 PD30 BMS PB8 PB30 DDR_D2 PB21 PB23 HHSDPA HFSDPA PA27 PA29 PA28
Table 4-1.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 PC27 PC28 PC25 PC20 PC12 PC7 PC5 PC0
Signal Name
NWR3/NBS3 NCS0 DQS0 RAS SDCK NSDCK D7 DDR_VREF D0 A14 PC31 PC29 PC30 PC22 PC17 PC10 PC11 PC2 SDA10 A17/BA1 DQM0 SDCKE D12 D8 D4 D3 A15 A13 XIN32 GNDANA WKUP PC26 PC21 PC15 PC9 PC3 NWR0/NWE A16/BA0 CAS D15
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AT91SAM9M11
Table 4-1.
Pin C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E5 E6 E7 E8 E9 D10 D6 D2 GNDIOM A18 A12 XOUT32 PD20 GNDBU VDDBU PC24 PC18 PC13 PC6 NWR1/NBS1 NANDOE DQM1 D14 D9 D5 D1 VDDIOM1 A11 A10 PD21 TSADVREF VDDANA JTAGSEL TST PC23 PC16 PC8 PC1
AT91SAM9M11 Pinout for 324-ball BGA Package (Continued)
Pin H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 Signal Name PE13 PE5 PE7 PE9 PE10 GNDCORE GNDIOP VDDCORE GNDIOM GNDIOM DDR_CS DDR_WE DDR_DQM1 DDR_CAS DDR_NCLK PE19 PE16 PE14 PE15 PE12 PE17 PE18 PE20 GNDCORE GNDCORE GNDIOP GNDIOM GNDIOM DDR_A12 DDR_A13 DDR_CKE DDR_RAS DDR_CLK Pin M13 M14 M15 M16 M17 M18 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 P1 P2 P3 P4 P5 P6 P7 P8 P9 Signal Name PB27 VDDIOM0 DDR_D14 DDR_D15 DDR_A0 DDR_A2 PA3 PA9 PA12 PA15 PA16 PA17 PB18 PD6 PD16 NTRST PB9 PB24 PB28 DDR_D13 DDR_D8 DDR_D9 DDR_D11 DDR_D12 PA11 PA13 PA19 PA21 PA23 PB12 PB19 PD8 PD28 Pin U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Signal Name PB3 PB7 PB17 PD7 PD10 PD14 TCK VDDOSC GNDOSC PB10 PB26 HHSDPB/DHSDP HHSDMB/DHSDM GNDUTMI VDDUTMIC PA31 PB1 PB2 PB5 PB15 PD3 PD5 PD12 PD17 TDO XOUT XIN VDDPLLUTMI VDDIOP2 HFSDPB/DFSDP HFSDMB/DFSDM VDDUTMII VBG
Signal Name
13
6437BS-ATARM-26-Apr-10
5. Power Considerations
5.1 Power Supplies
The AT91SAM9M11 has several types of power supply pins: * VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical. * VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). * VDDIOM1 pins: Power the External Bus Interface 1 I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V typical). * VDDIOP0, VDDIOP1, VDDIOP2 pins: Power the Peripherals I/O lines; voltage ranges from 1.65V to 3.6V. * VDDBU pin: Powers the Slow Clock oscillator, the internal RC oscillator and a part of the System Controller; voltage ranges from 1.8V to 3.6V. * VDDPLLUTMI Powers the PLLUTMI cell; voltage range from 0.9V to 1.1V. * VDDUTMIC pin: Powers the USB device and host UTMI+ core; voltage range from 0.9V to 1.1V, 1.0V typical. * VDDUTMII pin: Powers the USB device and host UTMI+ interface; voltage range from 3.0V to 3.6V, 3.3V typical. * VDDPLLA pin: Powers the PLLA cell; voltage ranges from 0.9V to 1.1V. * VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 1.65V to 3.6V * VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V to 3.6V, 3.3V typical. Ground pins GND are common to VDDIOM0, VDDIOM1, VDDIOP0, VDDIOP1 and VDDIOP2 power supplies. Separated ground pins are provided for VDDUTMIC, VDDUTMII, VDDBU, VDDOSC, VDDPLLA, VDDPLLUTMI and VDDANA. These ground pins are respectively GNDUTMIC, GNDUTMII, GNDBU, GNDOSC, GNDPLLA, GNDPLLUTMI and GNDANA.
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6. Processor and Architecture
6.1 ARM926EJ-S Processor
* RISC Processor Based on ARM v5TEJ Architecture with DSP Instruction Extensions and Jazelle(R) technology for Java(R) acceleration * Two Instruction Sets - ARM High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set * 5-Stage Pipeline Architecture: - Instruction Fetch (F) - Instruction Decode (D) - Execute (E) - Data Memory (M) - Register Write (W) * 32-KByte Data Cache, 32-KByte Instruction Cache - Virtually-addressed 4-way Associative Cache - Eight words per line - Write-through and Write-back Operation - Pseudo-random or Round-robin Replacement * Write Buffer - Main Write Buffer with 16-word Data Buffer and 4-address Buffer - DCache Write-back Buffer with 8-word Entries and a Single Address Entry - Software Control Drain * Standard ARM v4 and v5 Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for large pages and small pages can be specified separately for each quarter of the page - 16 embedded domains * Bus Interface Unit (BIU) - Arbitrates and Schedules AHB Requests - Separate Masters for both instruction and data access providing complete Matrix system flexibility - Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface - On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) * TCM Interface
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6.2
Bus Matrix
* 12-layer Matrix, handling requests from 11 masters * Programmable Arbitration strategy - Fixed-priority Arbitration - Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master * Burst Management - Breaking with Slot Cycle Limit Support - Undefined Burst Length Support * One Address Decoder provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for internal flash boot, one after remap * Boot Mode Select - Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0 - Selection is made by General purpose NVM bit sampled at reset * Remap Command - Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash) - Allows Handling of Dynamic Exception Vectors
6.2.1
Matrix Masters The Bus Matrix of the AT91SAM9M11 manages Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 6-1.
Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 Master 6 Master 7 Master 8 Master 9 Master 10 Master 11
List of Bus Matrix Masters
ARM926TM Instruction ARM926 Data Peripheral DMA Controller (PDC) USB HOST OHCI DMA DMA ISI Controller DMA LCD DMA Ethernet MAC DMA USB Device High Speed DMA USB Host High Speed EHCI DMA Video Decoder
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6.2.2 Matrix Slaves Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed. Table 6-2.
Slave 0
List of Bus Matrix Slaves
Internal SRAM Internal ROM USB OHCI USB EHCI
Slave 1 UDP High Speed RAM LCD User Interface Video Decoder Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3 External Bus Interface Internal Peripherals
6.2.3
Masters to Slaves Access All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and shown as "-" in the following tables. The four DDR ports are connected differently according to the application device. The user can disable the Video Decoder in the Video Mode Configuration Register (bit VDEC_SEL) in the Chip Configuration User Interface. * When the Video Decoder is not enabled (VDEC_SEL=0), the ARM instruction and data are
respectively connected to DDR Port 0 and DDR Port 1. The other masters share DDR Port 2 and DDR Port 3.
* When the Video Decoder is enabled (VDEC_SEL=1), DDR Port 0 is dedicated to the video
controller, and DDR Port 1 to the LCD controller. The remaining masters share DDR Port 2 and DDR Port 3.
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Figure 6-1.
Video Mode Configuration
VDEC_EN
Video LCD Decoder
+
Post Processing
DDR_S0
DMA
ARM I
DDR_S1
ARM D
ARM D
MATRIX DDR_S3
ARM I
VDEC_EN
DDR_S2
Table 6-3.
Master Slave
0 Internal SRAM 0 Internal ROM UHP OHCI UHP EHCI LCD User Int. UDPHS RAM 1 2 3 4 5 6 7 VDEC DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3 EBI Internal Periph. 0 ARM 926 Instr. X X X X X X X X X X 1 ARM 926 Data X X X X X X X X X X
AT91SAM9M11 Masters to Slaves Access with VDEC_SEL = 0
2 3 USB Host OHCI X X X X 4&5 6 ISI DMA X X X X X DMA X X X X 7 LCD DMA X X 8 9 USB Device HS X X X X X 10 USB Host EHCI X X X X 11
PDC X X X X X X
Ethernet MAC X X X X -
VDEC X X -
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Table 6-4.
Master 0 ARM Slave 0 Internal SRAM 0 Internal ROM UHP OHCI UHP EHCI 1 LCD User Int. UDPHS RAM VDEC 2 3 4 5 6 7 DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3 EBI Internal Periph. X X X X X X X X X X X X 926 Instr. X X X X 1 ARM 926 Data X X X X
AT91SAM9M11 Masters to Slaves Access with VDEC_SEL = 1 (default)
2 3 USB HOST OHCI X X X X 4&5 6 ISI DMA X X X X X DMA X X X X 7 LCD DMA X X 8 9 USB Device HS X X X X X 10 USB Host EHCI X X X X 11
PDC X X X X X X
Ethern et MAC X X X X -
VDEC X X -
Table 6-5 summarizes the Slave Memory Mapping for each connected Master, depending on the Remap status (RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and the BMS state at reset. Table 6-5. Internal Memory Mapping
Master Slave Base Address 0x0000 0000 RCBx = 0 RCBx = 1 Internal SRAM
BMS = 1
Internal ROM
BMS = 0
EBI NCS0
6.3
Peripheral DMA Controller (PDC)
* Acting as one AHB Bus Matrix Master * Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. * Next Pointer support, prevents strong real-time constraints on buffer management.
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The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): Table 6-6. Peripheral DMA Controller
Channel T/R Transmit Transmit Transmit Transmit Transmit Transmit Transmit Transmit Transmit Transmit Receive Receive Receive Receive Receive Receive Receive Receive Receive Receive Receive
Instance name DBGU USART3 USART2 USART1 USART0 AC97 SPI1 SPI0 SSC1 SSC0 TSDAC DBGU USART3 USART2 USART1 USART0 AC97 SPI1 SPI0 SSC1 SSC0
6.4
USB
The AT91SAM9M11 features USB communication ports as follows: * 2 Ports USB Host full speed OHCI and High speed EHCI * 1 Device High speed USB Host Port A is directly connected to the first UTMI transceiver. The Host Port B is multiplexed with the USB device High speed and connected to the second UTMI port. The selection between Host Port B and USB device high speed is controlled by a the bit UDPHS enable bit located in the UDPHS_CTRL control register.
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Figure 6-2. USB Selection
HS Transceiver HS Transceiver
EN_UDPHS 0 PA HS EHCI FS OHCI DMA PB HS USB 1
DMA
6.5
DMA Controller
* Two Masters * Embeds 8 channels * 64 bytes/FIFO for Channel Buffering * Linked List support with Status Write Back operation at End of Transfer * Word, HalfWord, Byte transfer support. * memory to memory transfer * Peripheral to memory * Memory to peripheral The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below. The hardware interface numbers are also given below in Table Table 6-7. DMA Channel Definition
T/R TX/RX TX RX TX RX TX RX TX RX TX RX TX/RX DMA Channel HW interface Number 0 1 2 3 4 5 6 7 8 9 10 13
Instance Name MCI0 SPI0 SPI0 SPI1 SPI1 SSC0 SSC0 SSC1 SSC1 AC97 AC97 MCI1
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6.6
Debug and Test Features
* ARM926 Real-time In-circuit Emulator - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel * Debug Unit - Two-pin UART - Debug Communication Channel Interrupt Handling - Chip ID Register * IEEE1149.1 JTAG Boundary-scan on All Digital Pins.
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7. Memories
Figure 7-1. AT91SAM9M11 Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF
Internal Memory Mapping
0x0000 0000 0x0010 0000
Boot Memory (1) ITCM(2) DTCM(2) SRAM ROM LCD User Interface UDPHS RAM UHP OHCI UHP EHCI 1 MBytes 1 MBytes 1 MBytes 1 MBytes 1 MBytes 1 MBytes 1 MBytes 1 MBytes 1 MBytes 1 MBytes
256M Bytes
0x1000 0000 EBI Chip Select 0
0x1FFF FFFF
0x0020 0000 Notes: (1) Can be ROM, EBI1_NCS0 or SRAM 0x0030 0000 depending on BMS and REMAP (2) Software programmable 0x0050 0000
0x0040 0000
256M Bytes
0x0060 0000
0x2000 0000
EBI Chip Select 1/ DDRSDRC1
0x0070 0000
256M Bytes
0xF000 0000
Peripheral Mapping Reserved
0x0080 0000 0x0090 0000 0x00A0 0000 16K Bytes 0x0FFF FFFF
0x2FFF FFFF
VDEC Undefined (Abort)
0x3000 0000 EBI Chip Select 2
0x3FFF FFFF 0xFFF7 8000
256M Bytes
0xFFF7 C000
UDPHS TCO, TC1, TC2
0x4000 0000 EBI Chip Select 3/ NANDFlash
0x4FFF FFFF
16K Bytes
256M Bytes
0xFFF8 0000 MCI0 0xFFF8 4000 16K Bytes
0x5000 0000
0x5FFF FFFF
EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 DDRSDRC0 Chip Select
256M Bytes
TWI0 0xFFF8 8000 TWI1 0xFFF8 C000
16K Bytes
0x6000 0000
16K Bytes
System Controller Mapping
0xFFFF C000
256M Bytes
0xFFF9 0000
USART0
16K Bytes
Reserved
0xFFFF E200
0x6FFF FFFF
0x7000 0000 256M Bytes
0xFFF9 4000
USART1
16K Bytes
ECC
USART2 16K Bytes 0xFFFF E400
512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 bytes 512 bytes 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes
0x7FFF FFFF
DDRSDRC1
0xFFFF E600
0x8000 0000
0xFFF9 8000 USART3 0xFFF9 C000 SSC0 0xFFFA 0000 SSC1 0xFFFA 4000 SPI0 0xFFFA 8000 SPI1 0xFFFA C000 AC97 0xFFFB 0000 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes
DDRSDRC0
0xFFFF E800
SMC
0xFFFF EA00
MATRIX
0xFFFF EC00
DMAC
0xFFFF EE00
DBGU
0xFFFF F000
AIC
0xFFFF F200
PIOA
0xFFFF F400
Undefined (Abort)
PIOB
TSADC 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FD10 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF F600
1,792M Bytes
0xFFFB 4000
PIOC ISI
0xFFFF F800
0xFFFB 8000 PWMC 0xFFFB C000 EMAC 0xFFFC 0000 0xFFFF FA00
PIOD PIOE
0xFFFF FC00 0xFFFF FD00
PMC RSTC SHDC
AES
0xFFFC 4000
TDES
0xFFFC 8000
0xFFFF FD20
RTTC SHA
0xFFFF FD30
0xFFFC C000
PITC
0xFFFF FD40
TRNG
0xFFFD 0000 0xEFFF FFFF MCI1 0xFFFD 4000 TC3, TC4, TC5
WDTC
0xFFFF FD50 0xFFFF FD60 0xFFFF FD70 0xFFFF FDB0
SCKCR GPBR Reserved RTCC Reserved
0xF000 0000 Internal Peripherals
0xFFFF FFFF
256M Bytes
0xFFFD 8000
Reserved
0xFFFF C000 SYSC 0xFFFF FFFF
0xFFFF FDC0 0xFFFF FFFF
16 Bytes
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7.1
Memory Mapping
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects NCS0 to NCS5. The bank 7 is directed to the DDRSDRC0 that associates this bank to DDR_NCS chip select and so dedicated to the 4-port DDR2/ LPDDR controller. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. The bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access.
7.2
7.2.1
Embedded Memories
Internal SRAM The AT91SAM9M11 product embeds a total of 64 Kbytes high-speed SRAM split in 4 blocks of 16 KBytes connected to one slave of the matrix. After reset and until the Remap Command is performed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. After Remap, the SRAM also becomes available at address 0x0. Figure 7-2. Internal SRAM Reset
RAM RAM
Remap 64K 64K
0x00300000
0x00000000
The AT91SAM9M11 device embeds two memory features. The processor Tightly Coupled Memory Interface (TCM) that allows the processor to access the memory up to processor speed (PCK) and the interface on the AHB side allowing masters to access the memory at AHB speed (MCK). A wait state is necessary to access the TCM at 400 MHz. Setting the bit NWS_TCM in the bus Matrix TCM Configuration Register of the matrix inserts a wait state on the ITCM and DTCM accesses.
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7.2.2 TCM Interface On the processor side, this Internal SRAM can be allocated to two areas. * Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR configuration register located in the Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Masters and by the AHB Masters through the AHB bus * Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus. * Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 64 Kbyte SRAM size available, the amount of memory assigned to each block is software programmable according to Table 7-1.
Table 7-1.
ITCM and DTCM Memory Configuration
SRAM B DTCM size (KBytes) seen at 0x200000 through AHB 0 64 32 SRAM C (KBytes) seen at 0x300000 through AHB 64 0 0
SRAM A ITCM size (KBytes) seen at 0x100000 through AHB 0 0 32
7.2.3
Internal ROM The AT91SAM9M11 embeds an Internal ROM, which contains the bootrom and SAM-BA program. At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset and before the Remap Command.
7.2.4
Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities the memory layout can be changed with two parameters. REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This is done by software once the system has boot. BMS allows the user to lay out to 0x0, when convenient, the ROM or an external memory. This is done by a hardware way at reset. Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The AT91SAM9M11 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. If BMS is detected at 1, the boot memory is the embedded ROM.
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If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 7.2.4.1 BMS = 1, boot on embedded ROM The system boots on Boot Program. * Boot on on-chip RC * Enable the 32768 Hz oscillator * Auto baudrate detection * Downloads and runs an application from external storage media into internal SRAM * Downloaded code size depends on embedded SRAM size * Automatic detection of valid application * Bootloader on a non-volatile memory - SPI DataFlash/SerialFlash connected on NPCS0 of the SPI0 - SDCard - NandFlash - EEPROM connected on TWI0 * SAM-BA Boot in case no valid program is detected in external NVM, supporting - Serial communication on a DBGU - USB Device HS Port 7.2.4.2 BMS = 0, boot on external memory * Boot on on-chip RC * Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. For optimization purpose, nothing else is done. To speed up the boot sequence user programmed software should perform a complete configuration: * Enable the 32768 Hz oscillator if best accuracy needed * Program the PMC (main oscillator enable or bypass mode) * Program and Start the PLL * Reprogram the SMC setup, cycle, hold, mode timings registers for EBI CS0 to adapt them to the new clock * Switch the main clock to the new value
7.3
External Memories
The AT91SAM9M11 features a Multi-port DDR2 Interface and an External Bus Interface allowing to connect to a wide range of external memories and to any parallel peripheral.
7.3.1
DDRSDRC0 Multi-port DDRSDR Controller Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes Transaction Latency. * Supports AHB Transfers: - Word, Half Word, Byte Access. * Supports DDR2, LPDDR
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* Numerous Configurations Supported - 2K, 4K, 8K, 16K Row Address Memory Parts - DDR2 with Four Internal Banks - DDR2/LPDDR with 16-bit Data Path - One Chip Select for DDR2/LPDDR Device (256 Mbytes Address Space) * Programming Facilities - Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of Transactions) - Timing Parameters Specified by Software - Automatic Refresh Operation, Refresh Rate is Programmable - Automatic Update of DS, TCR and PASR Parameters * Energy-saving Capabilities - Self-refresh, Power-down and Deep Power Modes Supported * Power-up Initialization by Software * CAS Latency of 2, 3 Supported * Reset function supported (DDR2) * Auto Precharge Command Not Used * On Die Termination not supported * OCD mode not supported 7.3.2 External Bus Interface * Integrates Three External Memory Controllers: - Static Memory Controller - DDR2/SDRAM Controller - SLC Nand Flash ECC Controller * Additional logic for NAND Flash and CompactFlashTM * Optional Full 32-bit External Data Bus * Up to 26-bit Address Bus (up to 64MBytes linear per chip select) * Up to 6 chip selects, Configurable Assignment: - Static Memory Controller on NCS0 - DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3, Optional NAND Flash support - Static Memory Controller on NCS4 - NCS5, Optional CompactFlashM support 7.3.2.1 Static Memory Controller * 8-, 16- or 32-bit Data Bus * Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) * Multiple device adaptability - Control signals programmable setup, pulse and hold time for each Memory Bank 27
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* Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time * Slow Clock mode supported 7.3.2.2 DDR2/SDR Controller * Supports DDR2/LPDDR2, SDR-SDRAM and LPSDR * Numerous Configurations Supported - 2K, 4K, 8K, 16K Row Address Memory Parts - SDRAM with Four Internal Banks - SDR-SDRAM with 16- or 32- bit Data Path - DDR2/LPDDR with 16- bit Data Path - One Chip Select for SDRAM Device (256 Mbyte Address Space) * Programming Facilities - Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of Transactions) - Timing Parameters Specified by Software - Automatic Refresh Operation, Refresh Rate is Programmable - Automatic Update of DS, TCR and PASR Parameters (LPSDR) * Energy-saving Capabilities - Self-refresh, Power-down and Deep Power Modes Supported * SDRAM Power-up Initialization by Software * CAS Latency of 2, 3 Supported * Auto Precharge Command Not Used * SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported - Clock Frequency Change in Precharge Power-down Mode Not Supported 7.3.2.3 NAND Flash Error Corrected Code Controller * Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select * Single bit error correction and 2-bit Random detection. * Automatic Hamming Code Calculation while writing - ECC value available in a register * Automatic Hamming Code Calculation while reading - Error Report, including error flag, correctable error flag and word address being detected erroneous - Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages
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8. System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories.
8.1
System Controller Mapping
The System Controller's peripherals are all mapped within the highest 16 KBytes of address space, between addresses 0xFFFF E800 and 0xFFFF FFFF. However, all the registers of the System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of 4 KB. Figure 8-1 on page 30 shows the System Controller block diagram. Figure 7-1 on page 23 shows the mapping of the User Interfaces of the System Controller peripherals.
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8.2
System Controller Block Diagram
AT91SAM9M11 System Controller Block Diagram
System Controller VDDCORE Powered irq0-irq2 fiq periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE POR por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK Real-Time Clock Real-Time Timer rtc_irq rtc_alarm rtt_irq rtt_alarm Debug Unit Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq
Figure 8-1.
dbgu_irq dbgu_txd pit_irq
proc_nreset PCK debug
jtag_nreset wdt_irq MCK periph_nreset
Boundary Scan TAP Controller
Bus Matrix
VDDBU
VDDBU POR UPLLCK UHP48M UHP12M periph_nreset periph_irq[25] USB High Speed Host Port
SLCK backup_nreset SLCK backup_nreset SLCK SHDN WKUP backup_nreset RC OSC XIN32 XOUT32 SLOW CLOCK OSC rtt0_alarm
Shut-Down Controller 4 General-purpose Backup Registers
UPLLCK USB High Speed Device Port
periph_nreset periph_irq[24]
SCKCR SLCK
XIN XOUT
int 12MHz MAIN OSC UPLL MAINCK Power Management Controller
UPLLCK
periph_clk[2..30] pck[0-1] UHP48M UHP12M PCK MCK DDR sysclk pmc_irq idle periph_clk[6..30]
PLLA periph_nreset
PLLACK
periph_nreset periph_nreset periph_clk[2..6] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD31 PE0-PE31 periph_irq[2..6] irq fiq dbgu_txd Embedded Peripherals periph_irq[6..30] in out enable
PIO Controllers
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8.3 Reset Controller
The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin output. It is capable to shape a reset signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a manual reset. The configuration of the Reset Controller is saved as supplied on VDDBU.
8.4
Shut Down Controller
The Shut Down Controller is supplied on VDDBU and allows a software-controllable shut down of the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the SHDN pin, and thus wakes up the system power supply.
8.5
Clock Generator
The Clock Generator is made up of: * One Low Power 32768 Hz Slow Clock Oscillator with bypass mode * One Low-Power RC oscillator * One 12 MHz Main Oscillator, which can be bypassed * One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the processor and to the peripherals. This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz. The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI macro.
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Figure 8-2.
Clock Generator Block Diagram
Clock Generator RCEN On Chip RC OSC XIN32 XOUT32 Slow Clock Oscillator
Slow Clock SLCK OSCSEL OSC32EN OSC32BYP
XIN XOUT
12M Main Oscillator
Main Clock MAINCK
UPLL
UPLLCK
PLLA and Divider
PLLA Clock PLLACK
Status
Control
Power Management Controller
8.6
Slow Clock Selection
The AT91SAM9M11 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an external slow clock on XIN32. The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respectively RCEN bit and OSC32EN bit in the system controller user interface. OSCSEL command selects the slow clock source. RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the slow clock control register (SCKCR) located at address 0xFFFFFD50 in the backup part of the system controller and so are preserved while VDDBU is present.
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Figure 8-3. Slow Clock
Clock Generator
RCEN
On Chip RC OSC Slow Clock SLCK XIN32 XOUT32 Slow Clock Oscillator OSCSEL OSC32EN OSC32BYP
After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0 allowing the system to start on the internal RC oscillator. The programmer controls by software the slow clock switching and so must take precautions during the switching phase. 8.6.1 Switch from Internal RC Oscillator to the 32768 Hz Crystal To switch from internal RC oscillator to the 32768 Hz crystal, the programmer must execute the following sequence: * Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator) through the Power Manage26-Apr-10ment Controller. * Enable the 32768 Hz oscillator by setting the bit OSCEN to 1. * Wait 32768 Hz startup time for clock stabilization (software loop). * Switch from internal RC to 32768 Hz by setting the bit OSCSEL to 1. * Wait 5 slow clock cycles for internal resynchronization. * Disable the RC oscillator by setting the bit RCEN to 0. 8.6.2 Bypass the 32768 Hz Oscillator The following step must be added to bypass the 32768 Hz Oscillator. * An external clock must be connected on XIN32. * Enable the bypass path OSC32BYP bit set to 1. * Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0. 8.6.3 Switch from 32768 Hz Crystal to the Internal RC Oscillator The same procedure must be followed to switch from 32768 Hz crystal to the internal RC oscillator. * Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator). * Enable the internal RC oscillator by setting the bit RCEN to 1. * Wait internal RC Startup Time for clock stabilization (software loop).
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* Switch from 32768 Hz oscillator to internal RC oscillator by setting the bit OSCSEL to 0. * Wait 5 slow clock cycles for internal resynchronization. * Disable the 32768Hz oscillator by setting the bit OSC32EN to 0.
8.7
Power Management Controller
The Power Management Controller provides all the clock signals to the system. PMC input clocks: * UPLLCK: From UTMI PLL * PLLACK From PLLA * SLCK: slow clock from OSC32K or internal RC OSC * MAINCK: from 12 MHz external oscillator PMC output clocks * Processor Clock PCK * Master Clock MCK, in particular to the Matrix and the memory interfaces. The divider can be 1,2,3 or 4 * DDR system clock equal to 2xMCK
Note: DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
* USB Host EHCI High speed clock (UPLLCK) * USB OHCI clocks (UHP48M and UHP12M) * Independent peripheral clocks, typically at the frequency of MCK * Two programmable clock outputs: PCK0 and PCK1 This allows the software control of five flexible operating modes: * Normal Mode, processor and peripherals running at a programmable frequency * Idle Mode, processor stopped waiting for an interrupt * Slow Clock Mode, processor and peripherals running at low frequency * Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt * Backup Mode, Main Power Supplies off, VDDBU powered by a battery
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Figure 8-4.
PLLACK
AT91SAM9M11 Power Management Controller Block Diagram
USBS USBDIV+1 /4
UHP48M UHP12M
USB OHCI USB EHCI
/1,/2
UPLLCK
Processor Clock Controller
Divider X /1 /1.5 /2
PCK int
SysClk DDR MCK Peripherals Clock Controller ON/OFF periph_clk[..]
MAINCK SLCK
Prescaler /1,/2,/4,.../64
/1 /2
/3 /4
Master Clock Controller
SLCK MAINCK UPLLCK
ON/OFF Prescaler /1,/2,/4,...,/64 Programmable Clock Controller pck[..]
8.7.1
Main Application Modes The Power Management Controller provides 3 main application modes. Normal Mode * PLLA and UPLL are running respectively at 400 MHz and 480 MHz * USB Device High Speed and Host EHCI High Speed operations are allowed * Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10) * System Input clock is PLLACK, PCK is 400 MHz * MDIV is `11', MCK is 133 MHz * DDR2 can be used at up to 133 MHz
8.7.1.1
8.7.1.2
USB HS and LP-DDR Mode * Only UPLL is running at 480 MHz, PLLA power consumption is saved * USB Device High Speed and Host EHCI High Speed operations are allowed * Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10) * System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz * MDIV is `01', MCK is 120 MHz * Only LP-DDR can be used at up to 120 MHz 35
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8.7.1.3
No UDP HS, UHP FS and DDR2 Mode * Only PLLA is running at 384 MHz, UPLL power consumption is saved * USB Device High Speed and Host EHCI High Speed operations are NOT allowed * Full Speed OHCI input clock is PLLACK, USBDIV is 7 (division by 8) * System Input clock is PLLACK, PCK is 384 MHz * MDIV is `11', MCK is 128 MHz * DDR2 can be used at up to 128 MHz
8.8
Periodic Interval Timer
* Includes a 20-bit Periodic Counter, with less than 1s accuracy * Includes a 12-bit Interval Overlay Counter * Real Time OS or Linux/WinCE compliant tick generator
8.9
Watchdog Timer
* 16-bit key-protected only-once-Programmable Counter * Windowed, prevents the processor to be in a dead-lock on the watchdog access
8.10
Real-Time Timer
* Real-Time Timer, allowing backup of time with different accuracies - 32-bit Free-running back-up Counter - Integrates a 16-bit programmable prescaler running on slow clock - Alarm Register capable to generate a wake-up of the system through the Shut Down Controller
8.11
Real Time Clock
* Low power consumption * Full asynchronous design * Two hundred year calendar * Programmable Periodic Interrupt * Alarm and update parallel load * Control of alarm and update Time/Calendar Data In
8.12
General-Purpose Backup Registers
* Four 32-bit backup general-purpose registers
8.13
Advanced Interrupt Controller
* Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor * Thirty-two individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) - Programmable Edge-triggered or Level-sensitive Internal Sources - Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
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* One External Sources plus the Fast Interrupt signal * 8-level Priority Controller - Drives the Normal Interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt * Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector * Protect Mode - Easy debugging by preventing automatic operations when protect modes are enabled * Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
8.14
Debug Unit
* Composed of two functions - Two-pin UART - Debug Communication Channel (DCC) support * Two-pin UART - Implemented features are 100% compatible with the standard Atmel USART - Independent receiver and transmitter with a common programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Support for two PDC channels with connection to receiver and transmitter * Debug Communication Channel Support - Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor's ICE Interface
8.15
Chip Identification
The AT91SAM9M11 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. * Chip ID: 0x819B05A1 * Ext ID: 0x00000001 * JTAG ID: 05B2_703F * ARM926 TAP ID: 0x0792603F
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8.16
PIO Controllers
* 5 PIO Controllers, PIOA, PIOB, PIOC, PIOD and PIOE, controlling a maximum of 160 I/O Lines * Each PIO Controller controls up to 32 programmable I/O Lines - PIOA has 32 I/O Lines - PIOB has 32 I/O Lines - PIOC has 32 I/O Lines - PIOD has 32 I/O Lines - PIOE has 32 I/O Lines * Fully programmable through Set/Clear Registers * Multiplexing of two peripheral functions per I/O Line * For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) - Input change interrupt - Glitch filter - Multi-drive option enables driving in open drain - Programmable pull up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time * Synchronous output, provides Set and Clear of several I/O lines in a single write
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9. Peripherals
9.1 Peripheral Mapping
As shown in Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space.
9.2
Peripheral Identifiers
Table 9-1 defines the Peripheral Identifiers of the AT91SAM9M11. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
Table 9-1.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
AT91SAM9M11 Peripheral Identifiers
Peripheral Mnemonic AIC SYS PIOA PIOB PIOC PIOD, PIOE TRNG USART0 USART1 USART2 USART3 MCI0 TWI0 TWI1 SPI0 SPI1 SSC0 SSC1 TC0 .. TC5 PWM TSADCC DMAC UHPHS LCDC AC97C EMAC ISI UDPHS AES, TDES, SHA Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D, Parallel I/O Controller E True Random Number Generator USART 0 USART 1 USART 2 USART 3 High Speed Multimedia Card Interface 0 Two-Wire Interface 0 Two-Wire Interface 1 Serial Peripheral Interface Serial Peripheral Interface Synchronous Serial Controller 0 Synchronous Serial Controller 1 Timer Counter 0 .. Timer Counter 5 Pulse Width Modulation Controller Touch Screen ADC Controller DMA Controller USB Host High Speed LCD Controller AC97 Controller Ethernet MAC Image Sensor Interface USB Device High Speed Advanced Encryption Standard, Triple Data Encryption Standard, Secure Hash Algorithm External Interrupt FIQ
Peripheral ID
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Table 9-1.
29 30 31
AT91SAM9M11 Peripheral Identifiers (Continued)
Peripheral Mnemonic MCI1 VDEC AIC Peripheral Name High Speed Multimedia Card Interface 1 Video Decoder Advanced Interrupt Controller IRQ External Interrupt
Peripheral ID
9.3
9.3.1
Peripheral Interrupts and Clock Control
System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: * the DDR2/LPDDR Controller * the Debug Unit * the Periodic Interval Timer * the Real-Time Timer * the Real-Time Clock * the Watchdog Timer * the Reset Controller * the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller.
9.3.2
External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.
9.4
Peripheral Signals Multiplexing on I/O Lines
The AT91SAM9M11 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplexes the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns "Function" and "Comments" have been inserted in this table for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral function which are output only, might be duplicated within the both tables. The column "Reset State" indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the "Reset State" column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. To amend EMC, programmable delay has been inserted on PIO lines able to run at high speed.
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9.4.1 Table 9-2.
I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
PIO Controller A Multiplexing Multiplexing on PIO Controller A (PIOA)
Peripheral A MCI0_CK MCI0_CDA MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_DA4 MCI0_DA5 MCI0_DA6 MCI0_DA7 ETX0 ETX1 ERX0 ERX1 ETXEN ERXDV ERXER ETXCK EMDC EMDIO TWD0 TWCK0 MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_DA4 MCI1_DA5 MCI1_DA6 MCI1_DA7 MCI1_CK SCK3 RTS3 CTS3 PWM3 TIOB2 ETXER ERXCK ECRS ECOL PCK0 Peripheral B TCLK3 TIOA3 TIOB3 TCKL4 TIOA4 TIOB4 ETX2 ETX3 ERX2 ERX3 Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function Comments
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9.4.2 Table 9-3.
I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31
PIO Controller B Multiplexing Multiplexing on PIO Controller B (PIOB)
Peripheral A SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TWD1 TWCK1 DRXD DTXD SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 RXD0 TXD0 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_VSYNC ISI_HSYNC ISI_MCK PCK1 CTS0 SCK0 RTS0 SPI0_NPCS1 SPI0_NPCS2 ISI_D8 ISI_D9 ISI_D10 ISI_D11 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 Function Comments
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9.4.3 Table 9-4.
I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
PIO Controller C Multiplexing Multiplexing on PIO Controller C (PIOC)
Peripheral A DQM2 DQM3 A19 A20 A21/NANDALE A22/NANDCLE A23 A24 CFCE1 CFCE2 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW NCS2 NCS3/NANDCS NWAIT D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 RTS2 TCLK2 CTS2 Peripheral B Reset State DQM2 DQM3 A19 A20 A21 A22 A23 A24 I/O I/O I/O I/O A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 Function Comments
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9.4.4 Table 9-5.
I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31
PIO Controller D Multiplexing Multiplexing on PIO Controller D (PIOD)
Peripheral A TK0 TF0 TD0 RD0 RK0 RF0 AC97RX AC97TX AC97FS AC97CK TD1 RD1 TK1 RK1 TF1 RF1 RTS1 CTS1 SPI1_NPCS2 SPI1_NPCS3 TIOA0 TIOA1 TIOA2 TCLK0 SPI0_NPCS1 SPI0_NPCS2 PCK0 PCK1 TSADTRG TCLK1 TIOB0 TIOB1 PWM0 PWM1 PWM2 SPI0_NPCS3 SPI1_NPCS1 SCK1 SCK2 PWM1 IRQ FIQ PCK0 TIOA5 TIOB5 TCLK5 Peripheral B PWM3 Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 TSAD0 TSAD1 TSAD2 TSAD3 GPAD4 GPAD5 GPAD6 GPAD7 Function Comments
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9.4.5 Table 9-6.
I/O Line PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31
PIO Controller E Multiplexing Multiplexing on PIO Controller E (PIOE)
Peripheral A LCDPWR LCDMOD LCDCC LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM2 PCK1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 Peripheral B PCK0 Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 Function Comments
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10. Embedded Peripherals
10.1 Serial Peripheral Interface (SPI)
* Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device
10.2
Two Wire Interface (TWI)
* Compatibility with standard two-wire serial memory * One, two or three bytes for slave address * Sequential read/write operations * Supports either master or slave modes * Compatible with Standard Two-wire Serial Memories * Master, Multi-master and Slave Mode Operation * Bit Rate: Up to 400 Kbits * General Call Supported in Slave mode * Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only - One Channel for the Receiver, One Channel for the Transmitter - Next Buffer Support
10.3
Universal Synchronous Asynchronous Receiver Transmitter (USART)
* Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first
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- Optional break generation and detection - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * IrDA modulation and demodulation - Communication at up to 115.2 Kbps * SPI Mode - Master or Slave - Serial Clock Programmable Phase and Polarity - SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/4 * LIN Mode - Compliant with LIN 1.3 and LIN 2.0 specifications - Master or Slave - Processing of frames with up to 256 data bytes - Response Data length can be configurable or defined automatically by the Identifier - Self synchronization in Slave node configuration - Automatic processing and verification of the "Synch Break" and the "Synch Field" - The "Synch Break" is detected even if it is partially superimposed with a data byte - Automatic Identifier parity calculation/sending and verification - Parity sending and verification can be disabled - Automatic Checksum calculation/sending and verification - Checksum sending and verification can be disabled - Support both "Classic" and "Enhanced" checksum types - Full LIN error checking and reporting - Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. - Generation of the Wakeup signal * Test Modes - Remote Loopback, Local Loopback, Automatic Echo
10.4
Serial Synchronous Controller (SSC)
* Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader,...) * Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal
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* Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
10.5
AC97 Controller
* Compatible with AC97 Component Specification V2.2 * Capable to Interface with a Single Analog Front end * Three independent RX Channels and three independent TX Channels - One RX and one TX channel dedicated to the AC97 Analog Front end control - One RX and one TX channel for data transfers, associated with a PDC - One RX and one TX channel for data transfers with no PDC * Time Slot Assigner allowing to assign up to 12 time slots to a channel * Channels support mono or stereo up to 20 bit sample length - Variable sampling rate AC97 Codec Interface (48KHz and below)
10.6
Timer Counter (TC)
* Three 16-bit Timer Counter Channels * Wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels
10.7
Pulse Width Modulation Controller (PWM)
* Four channels, one 16-bit counter per channel * Common clock generator, providing Thirteen Different Clocks - A Modulo n counter providing eleven clocks - Two independent Linear Dividers working on modulo n counter outputs * Independent channel programming - Independent Enable Disable Commands - Independent Clock Selection - Independent Period and Duty Cycle, with Double Buffering - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform
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10.8 High Speed Multimedia Card Interface (MCI)
* Compatibility with MultiMedia Card Specification Version 4.3 * Compatibility with SD Memory Card Specification Version 2.0 * Compatibility with SDIO Specification Version V2.0. * Compatibility with Memory Stick PRO * Compatibility with CE ATA
10.9
USB High Speed Host Port (UHPHS)
* Compliant with Enhanced HCI Rev 1.0 Specification - Compliant with USB V2.0 High-speed and Full-speed Specification - Supports Both High-speed 480Mbps and Full-speed 12 Mbps USB devices * Compliant with Open HCI Rev 1.0 Specification - Compliant with USB V2.0 Full-speed and Low-speed Specification - Supports Both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices * Root Hub Integrated with 2 Downstream USB Ports * Shared Embedded USB Transceivers
10.10 USB High Speed Device Port (UDPHS)
* USB V2.0 high-speed compliant, 480 MBits per second * Embedded USB V2.0 UTMI+ high-speed transceiver shared with UHP HS. * Embedded 4-KByte dual-port RAM for endpoints * Embedded 6 channels DMA controller * Suspend/Resume logic * Up to 2 or 3 banks for isochronous and bulk endpoints * Seven endpoints: - Endpoint 0: 64 bytes, 1 bank mode - Endpoint 1 & 2: 1024 bytes, 2 banks mode, High Bandwidth, DMA - Endpoint 3 & 4: 1024 bytes, 3 banks mode, DMA - Endpoint 5 & 6: 1024 bytes, 3 banks mode, High Bandwidth, DMA
10.11 LCD Controller (LCDC)
* Single and Dual scan color and monochrome passive STN LCD panels supported * Single scan active TFT LCD panels supported. * 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported * Up to 24-bit single scan TFT interfaces supported * Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays * 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN * 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN * 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT * Single clock domain architecture * Resolution supported up to 2048 x 2048
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10.12 Touch Screen Analog-to-Digital Converter (TSADC)
* 8-channel ADC * Support 4-wire resistive Touch Screen * 10-bit 384 Ksamples/sec. Successive Approximation Register ADC * -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity * Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs * External voltage reference for better accuracy on low voltage inputs * Individual enable and disable of each channel * Multiple trigger sources - Hardware or software trigger - External trigger pin * Sleep Mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels
10.13 Ethernet 10/100 MAC (EMAC)
* Compatibility with IEEE Standard 802.3 * 10 and 100 MBits per second data throughput capability * Full- and half-duplex operations * MII or RMII interface to the physical layer * Register Interface to address, data, status and control registers * DMA Interface, operating as a master on the Memory Controller * Interrupt generation to signal receive and transmit completion * 128-byte transmit and 128-byte receive FIFOs * Automatic pad and CRC generation on transmitted frames * Address checking logic to recognize four 48-bit addresses * Supports promiscuous mode where all valid frames are copied to memory * Supports physical layer management through MDIO interface * Supports Wake On Lan. The receiver supports Wake on LAN by detecting the following events on incoming receive frames: - Magic packet - ARP request to the device IP address - Specific address 1 filter match - Multicast hash filter match
10.14 Image Sensor Interface (ISI)
* ITU-R BT. 601/656 8-bit mode external interface support * Support for ITU-R BT.656-4 SAV and EAV synchronization * Vertical and horizontal resolutions up to 2048 x 2048 * Preview Path up to 640*480 * Support for packed data formatting for YCbCr 4:2:2 formats
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* Preview scaler to generate smaller size image
10.15 8-channel DMA (DMA)
* Acting as two Matrix Masters * Embeds 8 unidirectional channels with programmable priority * Address Generation - Source/Destination address programming - Address increment, decrement or no change - DMA chaining support for multiple non-contiguous data blocks through use of linked lists - Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of data into non-contiguous fields in system memory - Gather support for extracting fields from a system memory area into a contiguous transfer - User enabled auto-reloading of source, destination and control registers from initially programmed values at the end of a block transfer - Auto-loading of source, destination and control registers from system memory at end of block transfer in block chaining mode - Unaligned system address to data transfer width supported in hardware * Channel Buffering - 16-word FIFO - Automatic packing/unpacking of data to fit FIFO width * Channel Control - Programmable multiple transaction size for each channel - Support for cleanly disabling a channel without data loss - Suspend DMA operation - Programmable DMA lock transfer support * Transfer Initiation - Support for Software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface * Interrupt - Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple transaction completion or Error condition
10.16 True Random Number Generator (TRNG)
* Passed NIST Special Publication 800-22 Tests Suite * Passed Diehard Random Tests Suite * Provides a 32-bit Random Number Every 84 Clock Cycles * For 133 MHz Clock Frequency, Throughput Close to 50 Mbits/s
10.17 Advanced Encryption Standard (AES)
* Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
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* 256-bit Cryptographic Key * 16 Clock Cycles Encryption/Decryption Processing Time with a 256-bit Cryptographic Key * Support of the Five Standard Modes of Operation Specified in the NIST Special Publication 800- 38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques: - Electronic Code Book (ECB) - Cipher Block Chaining (CBC) - Cipher Feedback (CFB) - Output Feedback (OFB) - Counter (CTR) * 8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode * Last Output Data Mode Allows Optimized Message Authentication Code (MAC) Generation * Hardware Counter Measures against Differential Power Analysis Attacks * Connected to the DMA Controller to optimize Data Transfers for all Operating Modes - One Channel for the Receiver, One Channel for the Transmitter - Next Buffer Support
10.18 Triple Data Encryption Standard (TDES)
* Supports Single Data Encryption Standard (DES) and Triple Data Encryption Algorithm (TDEA or TDES) * Compliant with FIPS Publication 46-3, Data Encryption Standard (DES) * 64-bit Cryptographic Key for TDES * Two-key or Three-key Algorithms for TDES * 18-clock Cycles Encryption/Decryption Processing Time for DES * 50-clock Cycles Encryption/Decryption Processing Time for TDES * Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES Modes of Operation - Electronic Code Book (ECB) - Cipher Block Chaining (CBC) - Cipher Feedback (CFB) - Output Feedback (OFB) * 8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode * Last Output Data Mode Allows Optimized Message (Data) Authentication Code (MAC) Generation * Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes - One Channel for the Receiver, One Channel for the Transmitter - Next Buffer Support
10.19 Secure Hash Algorithm (SHA)
* Supports Secure Hash Algorithm (SHA1 and SHA256) * Compliant with FIPS Publication 180-2 * Configurable Processing Period:
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- 85 Clock Cycles to Maximize the Bandwidth for SHA1 or 386 Clock Cycles or Other Applications in PDC (Peripheral DMA) - 72 Clock Cycles to Maximize the Bandwidth for SHA256 or 265 Clock Cycles or Other Applications in PDC (Peripheral DMA) * Connection to PDC Channel Capabilities Optimizes Data Transfers - One Channel for the Transmitter - Next Buffer Support
10.20 Video Decoder (VDEC)
* Little-endian and Big-endian support. Decoder supported standards: * MPEG-4 Simple and Advanced Profile, levels 0-5 * H.264 Baseline Profile, levels 1-3.1 * H.263 Profile 0, levels 10-70 * VC-1 - Simple Profile, Low and Medium Levels - Main Profile, Low, Medium and High Levels - Advanced Profile, Levels 0-3 * MPEG-2 Main Profile, Low, Medium and High Levels * JPEG Profile Baseline DCT (sequential) and JFIF 1.02 file form Post-processor features: * Image up-scaling * Image down-scaling * YCbCr to RGB conversion * Dithering * Deinterlacing * Programmable alpha channel * Alpha blending * De-blocking filter for MPEG-4 simple profile/H.263 * Image cropping / digital zoom * Picture in picture * Supported display size for picture in picture * Image rotation
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11. Mechanical Characteristics
11.1 Package Drawings
Figure 11-1. 324-ball TFBGA Package Drawing
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12. AT91SAM9M11 Ordering Information
Table 12-1. AT91SAM9M11 Ordering Information
Package TFBGA324 Package Type Green Temperature Operating Range Industrial -40C to 85C
Ordering Code AT91SAM9M11-CU
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Revision History
Change Request Ref. RFO 7172
Doc. Rev 6437BS
Comments Section 10.20 "Video Decoder (VDEC)" added. `11-layer --> `12-layer' in Section 6.2 "Bus Matrix".
6437AS
First issue
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6437BS-ATARM-26-Apr-10

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